_____________________________________________________________________________________________________________________________ _________________ dsc2133 dsc2233 page 1 mk - q - b - p - d - 12050109 low - jitter i 2 c/spi programmable dual lvds oscillator datasheet dsc 2133 dsc 2233 general description the dsc 2133 and dsc2233 series of programmable, high - performance dual lvds oscillators utilizes a proven silicon mems technology to provide excellent jitter and stability while incorporating high output frequency flexibility . dsc21 33 and dsc2233 allow the user to independently modify the frequency of each output using i 2 c or spi interface , respectively . user can also select from two pre - programmed default output frequencies using the control pin. dsc2133 and dsc2233 are packaged in 14 - pin 3.2x2.5 mm qfn package and available in temperature grades from ext. commercial to industr ial. block diagram pin # dsc2 133 (i 2 c) dsc22 33 (spi) 3 nc sclk 5 sda mosi 6 scl miso 7 cs_bar ss features low rms phase jitter: <1 ps (typ) high stability: 25, 50 ppm wide temp erature range o industrial: - 40 to 85 c o ext. commercial: - 20 to 70 c high supply noise rejection: - 50 dbc two independent lvds outputs i 2 c/spi programmable frequencies short lead times: 2 weeks wide frequency range: o lvds output: 2.3 to 460 mhz miniature footprint of 3.2x2.5mm excellent shock & vibration immunity o qualified to mil - std - 883 high reliability o 20x better mtf than quartz oscillators supply range of 2.25 to 3.6 v lead free & rohs compliant applications storage area networks o sata, sas , fibre channel passive optical networks o epon, 10g - epon, gpon, 10g - pon ethernet o 1g, 10gbase - t/kr/lr/sr, and fcoe hd/sd/sdi video & surveillance pc i express
_____________________________________________________________________________________________________________________________ _________________ dsc2133 dsc2233 page 2 mk - q - b - p - d - 12050109 dsc2133 low - jitter i 2 c/spi programmable dual lvds oscillator dsc 2233 pin description pin no. pin name pin type description 1 enable i enables outputs when high and disables when low 2 nc na leave unconnected or grounded 3 nc na dsc2133: leave unconnected or grounded sclk i dsc2233: serial clock from master 4 gnd power ground 5 sda i dsc2133: i 2 c serial data mosi dsc2233: spi serial data from master to slave 6 scl i dsc2133: i 2 c serial clock miso o dsc2233: spi serial data from slave to master 7 cs_bar i dsc2133: i 2 c chip select (active low) ss i dsc2233: spi slave select (active low) 8 output1+ o positive lvds output 1 9 output1 - o negative lvds output 1 10 output 2 - o negative lvds output 2 11 output 2 + o positive lvds output 2 12 vdd 2 power power supply for lvds output 2 13 vdd power power supply 14 fs i default output clock frequency bit operational description the dsc2133/2233 is a dual lvds oscillator consisting of a mems resonator and a support pll ic . the outputs are generated through independent 8 - bit programmable dividers from the output of the internal pll. dsc2133/2233 allows for easy pro gramming of the output frequencies using i 2 c /spi interface. upon power - up, the initial output frequencies are controlled by an internal pre - programmed memory (otp). this memory stores all coefficients required by the pll for two different default frequency pairs . the contr ol pin (fs) selects the init ial pair . once the device is powered up, a new output frequency pair can be programmed. programming details are provided in the programming guide . standard default frequency pairs are described in the following sections. discera supports customer defined versions of the dsc2133/2233 . when enable (pin 1) is floated or connected to v dd , the dsc2133/2233 is in operational mode. driving enable to ground will tri - state both output drivers (hi - impedance mode).
_____________________________________________________________________________________________________________________________ _________________ dsc2133 dsc2233 page 3 mk - q - b - p - d - 12050109 dsc2133 low - jitter i 2 c/spi programmable dual lvds oscillator dsc 2233 output clock frequencies table 1 lists the standard default frequency configurations and the associated ordering information to be used in conjunction with the ordering code. customer defined combinations are available. table 1. pre - programmed p in - selectable output frequency pairs ordering info freq (mhz) select bit [fs] C default is [1] 0 1 g000 1 f out1 148.5 156.25 f out2 7 4.25 125 g0002 f out1 100 125 f out2 100 125 gxxxx f out1 contact factory for additional configurations. f out2 frequency select bit are weakly tied high so if left unconnected the defa ult setting will be [1] and the device will output the associated frequency highlighted in bold .
_____________________________________________________________________________________________________________________________ _________________ dsc2133 dsc2233 page 4 mk - q - b - p - d - 12050109 dsc2133 low - jitter i 2 c/spi programmable dual lvds oscillator dsc 2233 absolute maximum ratings item min max unit condition supply voltage - 0.3 +4.0 v input voltage - 0.3 v dd +0.3 v junction temp - +150 c storage temp - 55 +150 c soldering temp - +260 c 40 sec max. esd hbm mm cdm - 4000 400 1500 v note: 1000+ years of data retention on internal memory ordering code specifications (unless specified otherwise: t= 25 c) notes: 1. pin 4 v dd should be filtered with 0.01uf capacitor . 2. output is enabled if enable pad is floated or not connected. 3. t su is time to 100ppm stable output frequency after v dd is applied and outputs are enabled. 4. output waveform and test ci rcuit figures below define the parameters. 5. period jitter includes crosstalk from adjacent output. parameter condition min. typ. max. unit supply voltage 1 v dd 2.25 3.6 v supply current i dd en pin low C output s are d isabled 2 1 2 3 ma supply current 2 i dd en pin high C outputs are enabled r l = 10 0 , f o1 =f o2 = 1 56.25 mhz 38 ma frequency stability f includes frequency variations due to initial tolerance, temp. and power supply voltage 2 5 50 ppm aging f 1 year @ 25c 5 ppm startup time 3 t su t= 25c 5 ms input logic levels input logic hig h input logic low v ih v il 0.75 x v d d - - 0.25 x v dd v output disable time 4 t da 5 ns output enable time t en 20 n s pull - up resistor 2 pull - up exist s on all digital io 40 k lv ds outputs output offset voltage r=100 differential 1 .125 1.4 v delta offset voltage 50 mv pk to pk output swing single - ended 350 mv output transition time 4 rise time fall time t r t f 20% to 80% r l = 5 0 , c l = 2pf 2 00 ps frequency f 0 single frequency 2.3 4 60 mhz output duty cycle sym differential 4 8 5 2 % period jitter 5 j per f o 1 =f o2 = 156.25 mhz 2.5 ps rms integrated phase noise j cc 200khz to 20mhz @148.5 mhz 100khz to 20mhz @148.5 mhz 12khz to 20mhz @148.5 mhz 0.28 0.4 1. 7 2 ps rms dsc2 xxxxx freq (mhz) see freq. table - packing t: tape & reel : tube f i 2 package f : 3.2x2.5mm temp range e: - 20 to 70 i: - 40 to 85 stability 1: 50ppm 2: 25ppm t 33 1 prog mode 1 : i 2 c bus 2: spi bus
_____________________________________________________________________________________________________________________________ _________________ dsc2133 dsc2233 page 5 mk - q - b - p - d - 12050109 dsc2133 low - jitter i 2 c/spi programmable dual lvds oscillator dsc 2233 nominal performance parameters (unless specified otherwise: t=25 c, v dd =3.3 v ) lvds phase jitter (integrated phase noise) output waveform : lvds 350 mv 0.0 0.5 1.0 1.5 2.0 2.5 0 200 400 600 800 1000 phase jitter (ps rms) low - end of integration bw: x khz to 20 mhz 156mhz - lvds 212mhz - lvds 320mhz - lvds 410mhz - lvds v il 1/ f o output enable t da t en t f t r v ih 80 % 20% 50% output 830 mv
_____________________________________________________________________________________________________________________________ _________________ dsc2133 dsc2233 page 6 mk - q - b - p - d - 12050109 dsc2133 low - jitter i 2 c/spi programmable dual lvds oscillator dsc 2233 solder reflow profile package dimensions 3.2 x 2.5 mm 14 lead plastic package disclaimer: discera makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. disc era reserves the right to make changes without further notice to materials described herein. discera does not assume any liability arising from the application or use of any product or circuit described herein. discera does not authorize its products for use a critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of disceras product in a life - support systems application implies that the manufacture r assumes all risk of such use and in doing so indemnifies discera against all charges. discera, inc. 1961 concourse drive , san jose, california 95131 usa phone: +1 (408) 432 - 8600 fax: +1 (408) 432 - 8609 email: sales@discera.com www.discera.com msl 1 @ 260 c refer to jstd - 020c ramp - up rate (200 c to peak temp) 3 c/sec max. preheat time 150 c to 200 c 60 - 180 sec time maintained above 217 c 60 - 150 sec peak temperature 255 - 260 c time within 5 c of actual peak 20 - 40 sec ramp - down rate 6 c/sec max. time 25 c to peak temperature 8 min max. 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max. 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max.
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